As a semiconductor rectifier element in which on one principal surface of a semiconductor substrate including an N-type semiconductor layer, a cathode electrode is formed, and on the other principal surface, a rectangular-shaped anode region including a P-type semiconductor is formed, there is a PIN diode. The PIN diode achieves good breakdown voltage characteristics with respect to a reverse bias in such a way that the N-type semiconductor layer includes an N+ semiconductor layer and an N− semiconductor layer (intrinsic semiconductor layer) having lower impurity concentration than impurity concentration of the N+ semiconductor layer, and the N− semiconductor layer having high resistance is present between the anode region and the N+ semiconductor layer.
As a breakdown phenomenon that occurs when a reverse bias is applied, there is avalanche breakdown (electron avalanche breakdown). The avalanche breakdown occurs when a reverse bias exceeding a breakdown voltage (reverse breakdown voltage) is applied, and a temperature rise due to a large avalanche current flow may lead to thermal destruction of the element. It is known that a depletion layer that is generated in the N− semiconductor layer by applying a reverse bias is unlikely to extend in an end part of the anode region as compared with a central part of the anode region. That is, a thickness of the depletion layer is small in the end part of the anode region as compared with the central part, which is likely to give rise to electric field concentration, and therefore the above-described avalanche breakdown is likely to occur in the end part of the anode region. For this reason, there is proposed a technique that, by forming an annular P-type region surrounding the anode region, reduces the electric field concentration in the end part of the anode region to thereby improve avalanche resistance (see, for example, Patent Literatures 1 and 2).
FIG. 11 is a plan view illustrating a configuration example of a conventional PIN diode 100, in which an anode region 105 is surrounded by a plurality of FLRs104. FIG. 12 illustrates a cross section cut by an A10-A10 section line in FIG. 11. FIG. 13 is a cross-sectional view of the PIN diode without any FLR 104.
In the PIN diode 100, on one principal surface of a semiconductor substrate 101, a cathode electrode 110 is formed, and on the other principal surface, an anode region 105, two FLRs 104, and a stopper region 111 are formed. Each of the FLRs (Field Limiting Rings) 104 is an annular region that is formed along an outer edge of the anode region 105 and includes a P-type semiconductor, and referred to as a guard ring. The stopper region 111 is an annular region that is formed in a circumferential edge part of the semiconductor substrate 101 and includes an N+ semiconductor.
On the anode region 105, an anode electrode 106 is formed, and from a circumferential edge part of the anode region 105 to the stopper region 111, an oxide film 103 is formed. The oxide film 103 is an insulating film having an annular region, and the anode electrode 106 is formed with overlapping with an inner edge part of the oxide film 103, whereas with overlapping with an outer edge part, an annular equipotential electrode 102 is formed. The semiconductor substrate 101 includes an N+ semiconductor layer 101a and an N− semiconductor layer 101b, and by selectively diffusing P-type impurities from a surface of the N− semiconductor layer 101b, the anode region 105 and the FLRs 104 are formed.
In the case where the FLRs 104 are not provided, a depletion layer 112 formed by applying a reverse bias is tabular (planar plane) in a central part of the anode region 105, whereas in an end part B11 of the anode region 105, the depletion layer 112 is cylindrical. For this reason, in particular, in the end part B11 of a curved part B10, electric field concentration occurs, and thereby avalanche breakdown is likely to occur. On the other hand, in the case where the FLRs 104 are provided, the depletion layer 112 extends from the end part B11 of the anode region 105 toward an outer edge of the semiconductor substrate 101. That is, the depletion layer 112 extending from the end part B11 of the anode region 105 reaches the FLRs 104, and further extends toward the outside from there, and thereby an electric field in the end part B11 of the anode region 105 is reduced. Also, each of the FLRs 104 is electrically isolated from the anode region 105 or the other FLR 104, and therefore between the anode region 105 and the FLR 104, or between the FLRs 104, a voltage drop occurs toward the outside, so that in the FLR 104 parts, electric field concentration is unlikely to occur.
In general, when a surge voltage generated by an external cause such as an inductive load or leakage inductance due to primary-secondary coupling of a transformer exceeds a breakdown voltage, an avalanche current flows in an element. At this time, avalanche breakdown occurs from a location where an electric field is most concentrated in the element. For this reason, in the above-described PIN diode 100, the electric field concentration occurs in the curved part B10 at the outer edge of the anode region 105, and avalanche current flows to easily give rise to thermal destruction, so that there is a limitation in improving avalanche resistance.
According to a conventional technique search by the present inventors, it turns out that as a technique that improves avalanche resistance of a semiconductor device, there are: (1) a method that increases a P-type impurity diffusion depth; (2) a method that controls impurity concentration by multiple diffusion or ion implantation (e.g., Patent Literatures 1 and 3 to 9); (3) a method that forms a highly resistive film on a chip surface (e.g., Patent Literatures 2 and 10); and (4) a method that, outside an anode region, forms a plurality of annular regions having low impurity concentration (e.g., Patent Literature 1). The method (1) is one that, by increasing the diffusion depth at the time of diffusing P-type impurities to form an anode region, reduces electric field concentration in an end part of the anode region, but cannot prevent an electric field from being concentrated in a curved part of the anode region. Also, to increase the diffusion depth, time necessary for a diffusion process is increased, which gives rise to a problem of reducing productivity.
The method (2) is one that, by implanting ions that can serve as N-type impurities, such as phosphorous, arsenic, or antimony, into a surface part of a high concentration P layer to the extent of not exceeding P-type impurity concentration, or directly performing ion implantation of P-type impurities at low concentration, forms a highly resistive layer having reduced impurity concentration in an end part of an anode region, and the presence of the highly resistive layer prevents avalanche current from being attracted to a surface layer. This method cannot be also prevent an electric field from being concentrated in a curved part of the anode region, and requires an ion implantation process, which gives rise to a problem of reducing productivity. The method (3) is one in which an anode electrode is configured to have a plurality of electrodes that are mutually separated, and a connection between the electrodes is made by a highly resistive film, and a larger voltage drop at an outer electrode is used to reduce electric field concentration in an end part of an anode region. This method cannot be also prevent an electric field from being concentrated in a curved part of the anode region, and requires complicated patterning for forming the plurality of electrodes and also a process of forming the highly resistive film, and therefore there arises a problem of reducing productivity.
The method (4) is one that, outside the anode region, forms the plurality of annular regions having low impurity concentration such that the plurality of annular region overlap with each other in a surface part of a P layer, and thereby forms a resistive layer in an end part of the anode region. In this method, if avalanche breakdown occurs in a curved part of the anode region, avalanche current linearly flows toward an anode electrode through the resistive layer. At this time, the avalanche current flows with spreading, so that a sufficient voltage drop cannot be obtained, and therefore the avalanche breakdown continuously occurs at the same location. For this reason, the method (4) cannot prevent the curved part of the anode region from being thermally destroyed by the concentration of the avalanche current. Also, this method requires an ion implantation process for forming the annular regions having low concentration, and therefore there arises a problem of reducing productivity. Further, in the method (4), in the case of, in the curved part of the anode region, attempting to increase a resistance component in a direction toward the outside, more annular regions should be formed, and therefore there arises a problem of decreasing an effective chip area.